Sub-LVDS & CSI-2 on MachXO3L

Here are the questions:

  1. In the specification of MachXO3L, it is only mentioned that the FPGA supports LVDS33 and LVDS25. So is LVDS18 (Sub-LVDS) supported by the chip?
  2. If Sub-LVDS is supported, is the termination resistor on-chip or required off-chip?
  3. Does the CSI-2 output requires off-chip termination resistors?

1. Sub-LVDS Support

It turns out that it is perfectly fine to channel a Sub-LVDS output into a LVDS-compliant input terminal, as shown below.

subLVDS compatibility

subLVDS & LVDS specifications.png

2. Termination On-Chip?

Documentations of Lattice products are pretty scattered across the web. I managed to find the document MachXO3sysIOUsageGuide.pdf eventually.

The MachXO3™ PLD family sysIO™ buffers are designed to meet the needs of flexible I/O standards in today’s fast-paced design world. The supported I/O standards range from single-ended I/O standards to differential I/O standards so that users can easily interface their designs to standard buses, memory devices, video applications and emerging standards.

To my comfort, MachXO3 does comes with 100 Ohm terminations on selected pairs in certain banks (Bank 2). And indeed, Bank 2 is used in the Breakout Board provided by Lattice, for LVDS Rx.

MachOX3 100O

bank2 schematics

Conclusion, I do not need to add external resisters for this chip to receive LVDS singals. However the question remains on the requirement on SMA cable / PCB routing for LVDS lines.

3. CSI-2 Termination

For now, treat there is not need for termination, as they are build-in on both Lattice and i.MX6. Need to be confirmed with the manufacturers.



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