Some Research On MIPI CSI-2 and D-PHY

MIPI CSI-2 is based on a physical bus called D-PHY:

Featuring a differential clock and one to four differential data lines, the D-PHY is a center-aligned, source synchronous interface which is clocked on both the rising and falling edge.

There are two modes, HS (High Speed) and LP (Low Power):

Depending on the application, the HS mode may be utilized at all times or the D-PHY can switch from HS differential lanes to single ended. When the D-PHY is sending single ended data, this is called LP (Low Power) mode. In Camera and Display applications, LP is entered during the blanking period to reduce power. Additionally, in Display applications, LP mode is used for configuration of the screen.

Lattice MIPI D-PHY Interface IP

The DSI HS interface operates electrically as a Scalable-Low-Voltage-Signally (SLVS). The low logic voltage is 0V and high logic voltage is 400mV.

  Common Mode Voltage Voltage Swing Current Termination
LVDS 1.2 V 350mV 3.5mA 100 Ohm
SLVS 200mV 200mV 2mA? 100 Ohm?
Sub-LVDS
(SONY)
900mV 150mV 1.5mA 100 Ohm

 

 

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