Lattice Gearbox, and Sub-LVDS Bridge Reference Design

 

Input Gearbox – MachXO3 Family Data Sheet (2-19)

Each PIC on the bottom edge has a built-in 1:8 input gearbox. Each of these input gearboxes may be programmed as a 1:7 de-serializer or as one IDDRX4 (1:8) gearbox or as two IDDRX2 (1:4) gearboxes. Table 2-9 shows the gearbox signals.

More information on the input gearbox is available in TN1281, Implementing High-Speed Interfaces with MachXO3 Devices.

 

Gearing Distribution.png

Implementing High-Speed Interfaces with MachXO3 Devices page 1

 

The FPGA we are using is of grade 6 (highest)

LCMXO3L-6900C-6BG256C

subLVDS_to_CSI2

  • deser – from (no. channels) to (no. channels * 8)
  • sony_serial2parallel
    • word_aligner – align each channel to lane_width (8/10/12 bit) frame, with respective dvalid output (only channel 0 dvalied is in use)
    • data   = {lane9, lane8, lane7, lane6, lane5, lane4, lane3, lane2, lane1, lane0};
    • parser – generate Frame Valid output (fv) and Line Valid output (lv), as well as dvalid_out. the output is pixel data
  • csi2_tx –  take in pixel data and valid outputs from parser

 

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