Sub-LVDS & CSI-2 Debugging on MachXO3L FPGA

Sub-LVDS Debugging


CSI-2 Debugging

To debug CSI-2, the first is to determine if the lane clock is working.

The CSI clock output is named DCK. Sadly, Lattice Diamond prevents any connections between the DDR output (yes, DCK is a DDR output) to be connected to any I/O blocks (“cannot be packed in any I/O logic block” in the error description).

So the following assignment is illeagl:

assign test_csi_clk = DCK // which is eventally connected to counter + LED output

Therefore, the code is examined to find the next-best debugging signal.

Top (sublvds_to_csi2.v)
u_csi2_tx (.DCK(DCK), .sclk (sclk) … ) // DCK output, sclk input = 1/4 of LVDS clk
…..|– wire w_pixclk
…..|– u_pll_sonyclk_4lane ( .CLKI(w_pixclk), .CLKOP(CLKOP), .CLKOS(CLKOS),
…..|        .CLKOS2(byte_clk)…)
……        hs_clk_en(hs_clk_en), .hsxx_clk_en(hsxx_clk_en), .hs_data_en(hs_data_en)…)
………..|– u_oDDRx4 (.clkop, .clkos, .clkout(hs_clk), .dout, .hsxx_clk_en(hsxx_clk_en) )
……………….|– ODDRX4B


  • u_csi2_tx:
    the TX takes in sclk clock from the deserialiser deser. The clock frequency is one fourth (1/4) of the physical input LVDS clock 
  • w_pixclk:
    if reserved == 0, then

    assign w_pixclk  = sclk;


    w_pixclk  = internal oscillator

    in operation, reserved always == 0. so frequency of w_pixclk equals to sclk, or 1/4 of LVDS clk.

  • u_pll_sonyclk_4lane:
    the PLL block gives multipled clock, by a factor of 4, compared to w_pixclk. The two multiplied clocks CLKOP and CLKOS are offset by 90 degree of phase. CLKOS remains the same as the input.

    Ideally, CLKOP = CLKOS = LVDS clock in frequency
    byte_clk = 1/4 of LVDS clock in frequency
    This is where the data and clock is constructed for CSI TX.

    DCK = 1/4 of CLKOP WHEN hs_clk_en == 1
    If hs_data_en == 1, LP mode is off and hs mode is on (D[3:0] is transmitting)
  • u_oDDRx4
    Converts parallel data into serialised DDR outputs, without bother HS and LP yet. It consumes CLKOP and CLKOS to be used in ODDRX4B blocks. This means that the CSI TX and LVDS input shares the same data rate.
    there is an output clock clkout, follows CLKOS, when hsxx_clk_en == 1
    The output is a 4-channel dout register.



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