FPGA D-PHY Timing Constraints

 

w_pixclk = sclk = divide by 4 DDR Clock output (from deser to csi_tx)
so this is the byte clock

in the range of 60 ~ 70 MHz

 

CLKOP = CLKOS are bit clock = DDR Clock. in the range of 240 ~ 280 Mhz

 

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