csi2_tx Module Flow Chart

CSI Transmission Flow Chart

csi2_tx_Block Diagram.png

What has been verified…

  • The internal PLL x1 CLK is working fine (CLKOS_tx)
  • hs_data_en is functioning, turning on and off
  • This means that 99% the clock and data are working now, generating the pattern given in the simulation


CSI2TX_OP&OS clock.png

CLKOS lags CLKOP (PLL equivalent to CLK) by 90 degree.


  • byte_clk is the same as sclk
  • DCK follows hsxx_clk_en
  • D follows hs_data_en, otherwise it is Z
  • LPx is all 0 when hs_data_en is high



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