CSI Transmission Flow Chart
What has been verified…
- The internal PLL x1 CLK is working fine (CLKOS_tx)
- hs_data_en is functioning, turning on and off
- This means that 99% the clock and data are working now, generating the pattern given in the simulation
CLKOS lags CLKOP (PLL equivalent to CLK) by 90 degree.
parallel2byte
- byte_clk is the same as sclk
- DCK follows hsxx_clk_en
- D follows hs_data_en, otherwise it is Z
- LPx is all 0 when hs_data_en is high
huiminEE 