Deser Module Flow Chart

Flow Chart – from 4 lane DDR to parallel byte data (x4 Gearing)



Input data going to the DDR registers can optionally be delayed using the delay block, DELAYE. The 32-tap DELAYE block is used to compensate for clock injection delay times. The amount of the delay is determined by the software based on the type of interface implemented using the attribute DEL_MODE. Users are allowed to set the delay by choosing the USER_DEFINED mode for the block. When in USER_DEFINED mode, user must manually set the number of delay steps to be used. Each delay stay would generate ~105ps of delay. It is recommended to use the PREDEFINED mode for all generic DDR interfaces. If an incorrect attribute value is used for a given interface, the DELAYE setting will be incorrect and the performance of the DDR interface will not be optimal. The DELAYE block is applicable to the receive mode of the DDR interfaces. It is available for all input register paths at all sides of a MachXO3L/LF device.

– Implementing High-Speed Interfaces with MachXO3 Devices, p45

The purpose of adding and configuring the DELAYE is to match the propagation delay (injection time) of the clock input. The recommanded implementation is shown below:

DDR x4 Centered Interface RX.png

Interface rules:
• Must use a dedicated clock pin PCLK as the clock source for ECLKSYNCA
• Clock net routed to SCLK must use primary clock net
• Data input must use A/B pair of the I/O logic for x4 gearing
• DELAYE should be set to ECLK_CENTERED
• When DELAYD is used, one dynamic delay port is needed for the entire bus.
• This interface is supported at the bottom side of the devices


The MachXO3L/LF devices also have a dynamic edge clock synchronization control (ECLKSYNCA). This feature allows each edge clock to be disabled from core logic if desired. Designers can use this feature to synchronize the edge clock to an event or external signal if desired. Designers can also use this feature to design applications in which a clock and its associated logic can be dynamically disabled to save power.

ECLKSYNCA Definition.png

ECLKSYNCA element is associated with the ECLK and must be used to drive the ECLK.

– Implementing High-Speed Interfaces with MachXO3 Devices


Input for Generic DDR X4 Using 1:8 Gearing


 IDDRX4B Inst4_IDDRX4B0 (.D(dataini_t0), .ECLK(eclko), .SCLK(sclk_t), 
 .RST(reset), .ALIGNWD(alignwd), .Q0(q0_0), .Q1(q1_0), .Q2(q2_0), 
 .Q3(q3_0), .Q4(q4_0), .Q5(q5_0), .Q6(q6_0), .Q7(q7_0));

Q7 is the newest the data – LSB for Sony Singal

Q0 is the oldest data – MSB for Sony Singal

DDR x4 Timing.png

  • However, IDDRX4B will put the newest data to the MSB, therefore the byte data in the FPGA is fliped compared to orignal Sony LVDS data.
  • Also, there is a delay between the input and output, which is 2~3 byte delay
  • The parallel output is refreshed on the rising edge of the Byte Clock SCLK
  • The sampling may not start from the rising edge of the SCLK. Instead, it is dependent on UPDATE and SEL, which is controlled by ALIGNWD pin.

DDR x4 Circuit Design.png


This can be verified by simulation:

Deser_IDDRC4B Delay Sim.png

  • Green arrow shows one of the rising edge of the SCLK, which are used for parallel data update;
  • Blue lines show the internal fragmentation of the 8-bit data streams. This segmentation shall be random in real circuits;
  • Red arrow shows the delay from the first bit of data being present on the lane, to the time the whole data. If we count from the end of the lane data to the start of the parallel data, the delay is about 2 clock cycle, which is quite small. I believe the delay time should vary depends on the sampling timings
  • MSB:LSB – The Sony lane signals are transmitted with MSB first. Where as the IDDX4 assume the MSB is transmitted last. Therefore the signal is fliped, for example the 10-bit 0x03FF is fliped to 0xC0FF.



The Lane Clock (CLK) is directly fed into ECLK of the DDR X4 Gearing, through a  always-on ECLKSYNCA. We can call this Bit Clock.






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