sony_serial2parallel Moduel Flow Chart

Flow Chart- parallel byte data to parallel 10-bit data, aligned


(word aligner only works properly if the pixels between frames are multiple of four, see below)

Locking mechanism of dvalid_out

the word aligner blackbox has the ability to recognise Sony sync code to capture the currect framing / timing for the 10-bit data stream.


The recognision and locking seem to work for all sync code. For example, the word aligner could initialise its dvalid_out successfully with a EAV Invalid input.

Any of the sync code will trigger the dvalid_out generation successfully

One the other hand, partial sync code is rejected by the word aligner, to prove its robustnesss.

a simple 0xFFFh code will not tirgger dvalid_out


Inability to Re-sync after Dvalid_out Lock

Once dvalid_out is lock to a particular framing, it does not seem to adapt to futher sync code.

Below shows that a EAV invalid code: xx10 1101 1000 is not recognised by a previously erroneously lock dvalid_out. Since the dvalid_out is out of sync, the converter can never pick up the sync code again with correct framming. (in the illustration, the timing is ahead of time by 4 bit)

Sonyserial2parallel_dvalid failed to adapt.png

Possible Design Defect

The pixel number have to be multiple of 4, other wise the pixdata from the word aligner is incorrect and will hence distrupt the fv and lv generation.

The signal lv is not capturing the pixel infomation, every other line

It appears that the word aligner blackbox is badly design so it does not recognise the sync code at right time, of it does not come in exactly multiple of 4’s number of pixels after the previous sync code.

The workaround is to always ensure the transmission carries multiple of 4 of pixel for each line.

The second 0xFFFh sync code is not framed properlly, on the right side

In conclusion, the blank pixels and active pixels have to be multiple of FOUR in order for the lattice black box to function properly. 


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