Some Research On MIPI CSI-2 and D-PHY

MIPI CSI-2 is based on a physical bus called D-PHY:

Featuring a differential clock and one to four differential data lines, the D-PHY is a center-aligned, source synchronous interface which is clocked on both the rising and falling edge.

There are two modes, HS (High Speed) and LP (Low Power):

Depending on the application, the HS mode may be utilized at all times or the D-PHY can switch from HS differential lanes to single ended. When the D-PHY is sending single ended data, this is called LP (Low Power) mode. In Camera and Display applications, LP is entered during the blanking period to reduce power. Additionally, in Display applications, LP mode is used for configuration of the screen.

Lattice MIPI D-PHY Interface IP

The DSI HS interface operates electrically as a Scalable-Low-Voltage-Signally (SLVS). The low logic voltage is 0V and high logic voltage is 400mV.

  Common Mode Voltage Voltage Swing Current Termination
LVDS 1.2 V 350mV 3.5mA 100 Ohm
SLVS 200mV 200mV 2mA? 100 Ohm?
Sub-LVDS
(SONY)
900mV 150mV 1.5mA 100 Ohm

 

 

Register Access – Serial Communications

Serial Protocol

  • The Register Read/Write of the SONY Sensor can be done by either 4-wire (SPI) or I2C.
  • The determination of which protocol to be used it based on the 1st communication, and not possible to be changed thereafter until a sensor reset.
    • I2C – XCE must be held HIGH (disabling SPI communication (Slave Select))
    • [Unknown] – how does the 1st communication work??
  • SONY Documentation Page 26 to 34 for protocol definition

 

4-Wire Communication

As far as I understand, the 4-wire communication described in the documentation is SPI – Serial Peripheral Interface. It is omitted in our 2024 module this time, so below is a good introductory article about SPI protocol:

Introduction to Serial Peripheral Interface (SPI)

Essentially, there is a master (ARM processor) and a slave (sensor) with a LSB-first transfer.

Protocol Name Meaning SONY Pin Name Physical Socket (Pin)
CLK / SCK Serial Clock SCK SPI0_CLK (25)
MOSI Master Out / Slave In SDI SPI0_MOSI (26)
MISO Master In / Slave Out SDO SPI0_MISO (27)
SS Slave Select XCE SPI0_CSN (28)

[Unknown] – pin 33 & 34 has I2C / UART port, what is that for? pin 35 &36 are IR_CUT?

 

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I2C

This is also a LSB-first transfer (TAKE NOTE, the documentation is contradictory p.29 & p.31, so TAKE NOTE and do experiment out. It is suspected that this shouldbe MSB-first transfer)

Protocol Name Meaning SONY Pin Name Physical Socket (Pin)
SCL  Serial Data Communication Input SCK SPI0_CLK (25)
SDA  Serial Clock Input SDI SPI0_MOSI (26)

The Slave Address is: 0011010 + R/W

Register Communication Timing

There is a certain communication prohibied period, at the instant of Frame Update Timing. For registers marked “V” in the Register Map (p.35), they are updated at FUT. (Some “immediate” update registers can be set as well, while the rest must be set in standby mode.)

It is not obviously shown, but serial communication may NOT be allowed during Data Line frames. [TO VERIFY]

Register Holding (page 92)

This technique is used to stop the changes of register values to take effect immediately, by setting REGHOLD to 1.

IMX178 Sensor Board Pinout Diagram

IMX178 Sensor Board Pinout Diagram