Some Research On MIPI CSI-2 and D-PHY

MIPI CSI-2 is based on a physical bus called D-PHY: Featuring a differential clock and one to four differential data lines, the D-PHY is a center-aligned, source synchronous interface which is clocked on both the rising and falling edge. There are two modes, HS (High Speed) and LP (Low Power): Depending on the application, the …

Register Access – Serial Communications

Serial Protocol The Register Read/Write of the SONY Sensor can be done by either 4-wire (SPI) or I2C. The determination of which protocol to be used it based on the 1st communication, and not possible to be changed thereafter until a sensor reset. I2C - XCE must be held HIGH (disabling SPI communication (Slave Select)) …